1. Field of the Invention
The present invention relates to a multiphase clock generator, and more particularly, to a delay-locked loop-based multiphase clock generator.
2. Description of the Related Art
With increase of data processing speed of computers and digital communication equipments, multiphase clocks have been increasingly used for increasing operation band width. A multiphase clock can overcome a limitation on clock speed of a microprocessor and may be used to process data with a bit rate higher than an internal operation frequency in a communication system. Such a multiphase clock is being widely used for high performance VLSI systems.
In the meantime, conventional delay-locked loop-based multiphase clock generators use a plurality of multiphase clocks output from a voltage controlled delay line (VCDL) for generating clocks at a high speed.
However, these conventional delay-locked loop-based multiphase clock generators have a problem of harmonic lock that two inputs of a phase detector are locked to more than two periods and further a problem that output frequencies may not be correctly generated due to a layout mismatch and a delay mismatch of delay cells constituting a voltage controlled delay line, which is caused by change of process/power source voltage/temperature.
In addition, power source voltage noises are generated by parasitic inductance components existing in metal conductive lines which are in proportion to variation of current flowing through the lines. Therefore, if current flowing through a conductive line is suddenly changed due to a sudden change of an operation frequency, power source voltage noises are increased, which may result in deterioration of performance of the whole circuit.